In typical microprocessor programs, addresses are defined in terms of a base address and an offset address. The base address is the starting point for a block of data that the program uses and the offset address is the displacement of a specific data word from that base address. This allows programs to be generally applicable without regard to which portions of the physical memory are occupied with stored data. Thus a given memory fetch in a program is carried out using a virtual address made up of the base address plus an offset address. The process of generating a real physical address to memory corresponding to a given virtual address is referred to as address translation.
In current digital signal processors virtual memory address generation includes a two-step process: the addition of two 32-bit numbers, the base address and the address offset; and a step of ensuring that the calculated address stays within the range of a circular address buffer of designated size. The final result of that two-step operation is known as the virtual address. The traditional way of performing address translation yielding a real physical address is to first generate the virtual address, and then to perform an address translation step.
To describe the actual address manipulation included in virtual address generation and address translation, it is useful to start with an example system. Assume that the physical memory is made up of pages, each page containing 4 KB memory space. Address mapping is applied to the 20 MB of the virtual address to generate the 20-bit physical page address index. FIG. 1 illustrates a simple memory table format. Page address index address 101 includes bits 31 to 12. Page address 102 the address within a given page includes bits 11 to 0.
In current TI TMS320C6000 DSPs the D unit includes a full complement of hardware functions for addition, shifting, multiplexing and other processes involved in address generation and translation. FIG. 2 illustrates the D unit functionality for address translation. The D unit takes two source inputs, base address 201 stored in the base address register 203 and address offset 202 stored in the address offset register 204. The shift multiplexer 205 executes any required address shifts in the offset address. The D unit performs the 32-Bit add function in block 206 calculating the virtual address 207 based on the addressing mode. The remaining processing for address translation must be able to generate a virtual address in one of three possible addressing modes. The first mode is linear addressing; the remaining two modes comprehend two cases of circular addressing. Multiplexer 208 handles the masking required in the two circular modes utilizing a circular mask 212, which comes from program input 211. Following this masking step, the virtual address 207 is subjected to a comparison step in address translation block 209 to determine the physical address to memory 210.
The conventional solution for memory translation, illustrated in FIG. 2 takes these three cases into account but adds extra delay for the extra functions. After calculation of the virtual address, a table lookup/item comparison has to be applied in address translation block 209 to complete the physical address translation. The address calculation and translation implemented in this manner takes more than 20 levels of logic and cannot be accomplished in one clock cycle of a GHz CPU.
In addition to straightforward linear addressing, current DSP architectures define a circular addressing mode. As noted above, we assume that the physical memory is made up of pages, each page containing 4 KB memory space. Address mapping is applied to the 20 MSB of the virtual address to generate the 20-bit physical page address index.
Linear addressing is illustrated in FIG. 3. A virtual address index may be computed as the sum 303 of base address 301 and address offset 302. Further, as illustrated in FIG. 3, it is possible to construct a look-up table translating a specific virtual address (given in FIG. 3 as virtual address indices 0 to 7) to a corresponding physical address index. The traditional way of performing address translation is to generate the virtual address, and then to perform additional steps based on this virtual address. This multi-step process causes the overall address translation process to have severe speed limitations. Additional complications arise when circular address translation having added special cases must be comprehended.